A shift register is widely used to delay a serial signal and output the signal, or as one means for performing the serial to parallel conversion.
A shifting circuit used with the prior art shift register is constructed by flip-flop circuits employing NAND circuits or NOR circuits, or by flip-flop circuits having two latch circuits connected in series. For example, JP-A-2-105396 (1990) by Akiyama et al. discloses a shift register in which a plurality of memory cells each being constructed by two latch circuits are connected in series.
The shifting circuit constructed by such a flip-flop circuit requires for example about sixteen transistor devices per stage in the case where a master-slave flip-flop is used. Since the shift register is constructed by connecting such shifting circuits in series by the number of shifting stages, for example, in the case where the shift register having a thousand stages is manufactured, there is required one thousand flip-flop circuits or two thousand latch circuits. Therefore, the number of devices making up the shift resister becomes very enormous, so that the prior art shift register is not suitable for higher integration. This is one problem.
In addition, with the prior art shifting circuit, since almost all the elements are simultaneously operated, there arises another problem in that the power consumption when those elements are operated as the shift register is very large.